FPGA讨论组

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Verilog HDL中task与function的区别

by 永不止步步 65535次查看03-30 09:51

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NiosII: Pausing target processor: not responding

by 永不止步步 65535次查看03-28 10:55

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No Nios II target connection paths were located

by 永不止步步 65535次查看03-28 10:51

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RGB888 TO BT1120 转换

by 永不止步步 65535次查看03-28 10:47

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quartus错误整理

by 永不止步步 65535次查看03-23 11:21

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quartus_ii_常见的19个错误、28个警告

by 永不止步步 65535次查看03-23 11:20

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Verilog中generate的用法

by 永不止步步 65535次查看03-23 11:11

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verilog选择数据类型时常犯的错误

by 永不止步步 65535次查看03-23 11:05

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this signal is connected to multiple drivers

by 永不止步步 65535次查看03-18 15:14

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Cannot mix blocking and non blocking

by 永不止步步 65535次查看03-18 15:10

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在使用逻辑分析仪查看时钟时，采样时钟是看不了的。

by 永不止步步 65535次查看03-18 15:00

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FPGA面试宝典

by 永不止步步 65535次查看03-18 14:59